synchronous up/down counter pulse
clock input flip-flop steering logic
output
clock pulses input counting down counting up clear input to reset data input load input presetting carry output overflow borrow output underflow to trigger
low-to-high level transition
count (clock) input to enter data feature
module-N divider to modify the count length to cascade by feeding outputs
5
Study the text carefully. Use ex. 4.
— реверсивный счетчик
— импульс
— тактовый ход
— триггер
— управляющее логическое устройство
— выход
— вход тактовых импульсов
— вычитание
— сложение
— вход «очистка»
— сбросить, очистить
— вход данных
— вход загрузки
— предварительная установка
— выход «перенос»
— переполнение
— выход «заём»
— опустошение
— переключать
— перепад уровня с низкого на высокий (с 0 на 1)
— тактовый вход
—• закладывать данные
— характерная черта
— делитель частоты
— изменять длительность счета
— собирать в каскады
— путем подключения выходов
6
7
Read the words, point out those which deal with the topic “Inputs of Synchronous Counters” and write them out.
g) counter
h) available
i) to cascade
j) to preset-
k) overflow
l) underflow
m) to modify
n) to trigger
o) similarly
p) borrow
q) clock
r) count
s) to design
t) to consist
c) to use
a) input d) valve
b) data. e) output
f) pulse
u) steering
v) level
w) transition
x) reversible
y) clear
z) indication a>1>>2) to determine I/) low
c') logic
cT) independently
Read the word-combinations and point out those with Participles:
a) a varying amount; b) increasing the thickness; c) with their stators connected in series; d) being a trained technician; e) by using a valve? f) an instrument for measuring current; g) copper being a good conductor; h) having been adjusted; i) avoid wearing loose overalls; j) know about Franklin having worked in.
9 1
Read the sentences and point out numbers of those which deal with the topic “Synchronous Counters”.
1. The control pulses are generated from the supply voltage, which is supplied to the control pulse circuits via a transformer and a filter circuit. 2. The synchronous up/down counters consist of flip-flops and steering gear. 3. Comparison of the filtered a-c voltages and the input>1 signal to the control pulse circuits gives the phasing of the control
pulses. 4. The control pulses are then fed to a logic circuit which checks
that they are within set delay angle limits. 5. The output of all flip-flop^ are triggered by a low-to-high level transition of either count input.